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F
"PAX: A Datapath-Scalable Minimalist Cryptographic Processor for Mobile Devices",
Book chapter in Nadia Nedjah and Luiza de Macedo Mourelle eds., Embedded Cryptographic Hardware: Design and Security, New York, Nova Science Publisher, ISBN: 1-59454-145-0, Chapter 2, pp. 19-34, 2004 .
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"Workload Characterization of Elliptic Curve Cryptography and other Network Security Algorithms for Constrained Environments",
Proceedings of the 5th IEEE Annual Workshop on Workload Characterization (WWC-5), Austin, Texas, USA, pp. 127-137, Nov. 2002.
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"Performance Impact of Addressing Modes on Encryption Algorithms",
Proceedings of the International Conference on Computer Design (ICCD 2001), Austin, Texas, USA, pp. 542-545, Sept. 2001.
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"Butterfly and inverse Butterfly nets integration on Altera NioS-ii embedded processor",
44th IEEE Asilomar Conference on Signal, Systems and Computers, Pacific Grove, California, USA, November 2010.
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"Virtualization of a Processor-based Crypto-Protection Mechanism and Integration within a Separation Kernel Architecture",
Princeton University Department of Electrical Engineering Technical Report CE-L2006-006, November 2006.
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H
"A New Basis for Shifters in General-Purpose Processors for Existing and Advanced Bit Manipulations",
IEEE Transactions on Computing, vol. 58, issue 8, August 2009.
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"Accelerating the Whirlpool Hash Function Using Parallel Table Lookup and Fast Cyclical Permutation",
Proceedings of the 15th Fast Software Encryption Workshop (FSE), Lausanne, Switzerland, February 2008.
Abstract
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Fast Bit Matrix Multiplication in Commodity Microprocessors,
, Princeton University Department of Electrical Engineering Technical Report CE-L2007-011, November 2007.
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"Performing Advanced Bit Manipulations Efficiently in General-Purpose Processors",
Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH-18), Montpellier, France, pp. 251-260, June 2007.
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A New Basis for Shifters in General-Purpose Processors for Existing and Advanced Bit Manipulations,
, Princeton University Department of Electrical Engineering Technical Report CE-L2007-004, July 2007.
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Accelerating the Whirlpool Hash Function using On-Chip Lookup Tables,
, Princeton University Department of Electrical Engineering Technical Report CE-L2007-001, February 2007.
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Achieving Very Fast Bit Matrix Multiplication in Commodity Microprocessors,
, Princeton University Department of Electrical Engineering Technical Report CE-L2007-006, August 2007.
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"Fast Bit Compression and Expansion with Parallel Extract and Parallel Deposit Instructions",
Proceedings of the IEEE 17th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), pp. 65-72, 11/09/2006.
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"Comparing Fast Implementations of Bit Permutation Instructions",
Proceedings of the 38th Annual Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, pp. 1856-1863, Nov. 2004.
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"Architectural Support for Hypervisor-Secure Virtualization",
in Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 3–7, 2012.
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"Physical Attack Protection with Human-Secure Virtualization in Data Centers",
Workshop on Open Resilient human-aware Cyber-physical Systems (WORCS), June 25, 2012.
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"Rapid Single-Chip Secure Processor Prototyping on OpenSPARC FPGA Platform",
in Proceedings of the Rapid System Prototyping Symposium (RSP), May 24-27, 2011.
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"A Case for Hardware Protection of Guest VMs from Compromised Hypervisors in Cloud Computing",
in Proceedings of the Second International Workshop on Security and Privacy in Cloud Computing (SPCC), June 20-24, 2011.
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"Eliminating the Hypervisor Attack Surface for a More Secure Cloud",
in Proceedings of the Conference on Computer and Communications Security (CCS), Oct. 17-21, 2011.
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"Trust but Verify: Trust Evidence for Hypervisor-Secure Virtualization",
Princeton University Department of Electrical Engineering Technical Report CE-L2011-008, Nov. 16, 2011.
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"General-purpose FPGA Platform for Efficient Encryption and Hashing",
in Proceedings of the Application-specific Systems, Architectures and Processors conference, ASAP, July 7-9, 2010.
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"A Framework for Testing Hardware-Software Security Architectures",
Annual Computer Security Applications Conference, Austin, Texas USA, December 6 2010.
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"Evaluation of OpenSPARC FPGA Platform as a Security and Performance Research Platform",
Princeton University Department of Electrical Engineering Technical Report CE-L2010-002, Sept. 6, 2010.
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"A Framework for Testing Hardware-Software Security Architectures",
Princeton University Department of Electrical Engineering Technical Report CE-L2009-001, February 2009.
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"SP Reference Manual Addendum -- Secure Stacks for TSMs and Emulation of SP Interrupt Protection",
Princeton University Department of Electrical Engineering Technical Report CE-L2009-006, August 2009.
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