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"Last-Level Cache Side-Channel Attacks are Practical",
Proceedings of IEEE Symposium on Security and Privacy, San Jose, pp. 605-622, May 2015.
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"Can randomized mapping secure instruction caches from side-channel attacks?",
in Proceedings of the Workshop on Hardware and Architectural Support for Security and Privacy (HASP), Portland, June 13, 2015.
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"Random Fill Cache Architecture",
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture (Micro-47), Cambridge, pp. 203-215, December 2014.
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"Security Testing of a Secure Cache Design",
in Proceedings of the Workshop on Hardware and Architectural Support for Security and Privacy (HASP), June 24, 2013.
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"Adaptive and Dynamic Network Provisioning with Network Forensics Devices",
Princeton University Department of Electrical Engineering Technical Report CE-L2011-005, Sept. 15, 2011.
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"On-Chip Lookup Tables for Fast Symmetric-Key Encryption",
Proceedings of the IEEE 16th International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2005), Samos, Greece, pp. 356-363, July 23-25, 2005.
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"Fast Parallel Table Lookups to Accelerate Symmetric-Key Cryptography",
Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC 2005), Las Vegas, Nevada, USA, pp. 526-531, April 4-6, 2005.
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"Evaluating Instruction Set Extensions for Fast Arithmetic on Binary Finite Fields",
Proceedings of the International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2004), Galveston, Texas, USA, pp. 125-136, Sept. 2004.
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"Performance Scaling of Cryptography Operations in Servers and Mobile Clients",
Proceedings of the Workshop on Building Block Engine Architectures for Computer Networks (BEACON 2004), Boston, Massachusetts, USA, Oct. 2004.
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"Runtime Execution Monitoring (REM) to Detect and Prevent Malicious Code Execution",
Proceedings of the International Conference on Computer Design (ICCD 2004), San Jose, California, USA, pp. 452-457, Oct. 11-13, 2004.
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"PAX: A Datapath-Scalable Minimalist Cryptographic Processor for Mobile Devices",
Book chapter in Nadia Nedjah and Luiza de Macedo Mourelle eds., Embedded Cryptographic Hardware: Design and Security, New York, Nova Science Publisher, ISBN: 1-59454-145-0, Chapter 2, pp. 19-34, 2004 .
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"Workload Characterization of Elliptic Curve Cryptography and other Network Security Algorithms for Constrained Environments",
Proceedings of the 5th IEEE Annual Workshop on Workload Characterization (WWC-5), Austin, Texas, USA, pp. 127-137, Nov. 2002.
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"Performance Impact of Addressing Modes on Encryption Algorithms",
Proceedings of the International Conference on Computer Design (ICCD 2001), Austin, Texas, USA, pp. 542-545, Sept. 2001.
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"Smartphone Impostor Detection with Behavioral Data Privacy and Minimalist Hardware Support",
TinyML Research Symposium, 2021 .
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"SoK: Hardware Defenses Against Speculative Execution Attacks",
IEEE International Symposium on Secure and Private Execution Environment Design, 2021 .
Abstract
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"Position Paper: Consider Hardware-enhanced Defenses for Rootkit Attacks",
Proceedings of the 9th International Workshop on Hardware and Architectural Support for Security and Privacy (HASP), 2020 .
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"Butterfly and inverse Butterfly nets integration on Altera NioS-ii embedded processor",
44th IEEE Asilomar Conference on Signal, Systems and Computers, Pacific Grove, California, USA, November 2010.
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"Virtualization of a Processor-based Crypto-Protection Mechanism and Integration within a Separation Kernel Architecture",
Princeton University Department of Electrical Engineering Technical Report CE-L2006-006, November 2006.
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"Cloud Server Benchmark Suite for Evaluating New Hardware Architectures",
IEEE Computer Architecture Letters, July-Dec 2016.
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"A New Basis for Shifters in General-Purpose Processors for Existing and Advanced Bit Manipulations",
IEEE Transactions on Computing, vol. 58, issue 8, August 2009.
Abstract
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"Accelerating the Whirlpool Hash Function Using Parallel Table Lookup and Fast Cyclical Permutation",
Proceedings of the 15th Fast Software Encryption Workshop (FSE), Lausanne, Switzerland, February 2008.
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Fast Bit Matrix Multiplication in Commodity Microprocessors,
, Princeton University Department of Electrical Engineering Technical Report CE-L2007-011, November 2007.
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"Performing Advanced Bit Manipulations Efficiently in General-Purpose Processors",
Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH-18), Montpellier, France, pp. 251-260, June 2007.
Abstract
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A New Basis for Shifters in General-Purpose Processors for Existing and Advanced Bit Manipulations,
, Princeton University Department of Electrical Engineering Technical Report CE-L2007-004, July 2007.
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Accelerating the Whirlpool Hash Function using On-Chip Lookup Tables,
, Princeton University Department of Electrical Engineering Technical Report CE-L2007-001, February 2007.
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