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S
"SP-PAX: Hardware implementation of SP module with PAX cryptoprocessor",
Princeton University Department of Electrical Engineering Technical Report CE-L2008-006, April 2008.
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"Secure Key Management Architecture Against Sensor-node Fabrication Attacks",
IEEE GlobeCom 2007, Washington, DC, November 2007.
Abstract
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SP Processor Architecture Reference Manual,
, Princeton University Department of Electrical Engineering Technical Report CE-L2007-009, 11/21/2007.
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"Scope of DDoS Countermeasures: Taxonomy of Proposed Solutions and Design Goals for Real-World Deployment",
8th International Symposium on Systems and Information Security (SSI'2006), November 2006.
Abstract
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"Satisfiability-based Framework for Enabling Side-channel Attacks on Cryptographic Software",
Proceedings of the Conference on Design, Automation and Test in Europe (DATE 2006), Munich, Germany, pp. 18-23, March 2006.
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"Single-Cycle Bit Permutations with MOMR Execution",
Journal of Computer Science and Technology, vol. 20, issue 5, pp. 577-585, September 2005.
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"Security as a New Dimension in Embedded System Design",
Proceedings of the 41st Design Automation Conference (DAC 2004), San Diego, California, USA, pp. 753-760, June 2004.
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"Scoping Security Issues for Interactive Grids",
Proceedings of the 37th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, pp. 367-373, Nov. 2003.
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"Subword Sorting with Versatile Permutation Instructions",
Proceedings of the International Conference on Computer Design (ICCD 2002), Freiburg, Germany, pp. 234-241, Sept. 2002.
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"Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures",
Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2000), Boston, Massachusetts, USA, pp. 3-14, July 2000.
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R
"Record-Replay Architecture as a General Security Framework",
IEEE International Symposium on High-Performance Computer Architecture (HPCA), Vienna, Austria, IEEE, 24/02/2018.
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"Random Fill Cache Architecture",
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture (Micro-47), Cambridge, pp. 203-215, December 2014.
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"Rapid Single-Chip Secure Processor Prototyping on OpenSPARC FPGA Platform",
in Proceedings of the Rapid System Prototyping Symposium (RSP), May 24-27, 2011.
Abstract
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"Running Untrusted Applications on Sensitive Data",
Princeton University Department of Electrical Engineering Technical Report CE-L2011-007, Nov. 16, 2011.
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"Re-examining Probabilistic Versus Deterministic Key Management",
Proceedings of the 2007 IEEE International Symposium on Information Theory (ISIT), Nice, France, pp. 2586-2590, June 2007.
Abstract
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Resolving Encoding Issues in Combining PAX and PLX Instruction Sets,
, Princeton University Department of Electrical Engineering Technical Report CE-L2007-007, August 2007.
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"Runtime Execution Monitoring (REM) to Detect and Prevent Malicious Code Execution",
Proceedings of the International Conference on Computer Design (ICCD 2004), San Jose, California, USA, pp. 452-457, Oct. 11-13, 2004.
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"Refining Instruction Set Architecture for High-Performance Multimedia Processing in Constrained Environments",
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2002), San Jose, California, pp. 253-264, July 2002.
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"Quantification of De-anonymization Risks in Social Networks",
Information Systems Security and Privacy, Porto, 19/02/2017.
Abstract
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P
"Position Paper: Consider Hardware-enhanced Defenses for Rootkit Attacks",
Proceedings of the 9th International Workshop on Hardware and Architectural Support for Security and Privacy (HASP), 2020 .
Abstract
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"Power-Grid Controller Anomaly Detection with Enhanced Temporal Deep Learning",
IEEE International Conference on Trust, Security and Privacy in Computing and Communications (TrustCom), 05/08/2019.
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"Physical Attack Protection with Human-Secure Virtualization in Data Centers",
Workshop on Open Resilient human-aware Cyber-physical Systems (WORCS), June 25, 2012.
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"Processor Accelerator for AES",
Proceedings of the 2010 IEEE 8th Symposium on Application Specific Processors, Anaheim, CA, USA, pp. 71-76, June 13-14 2010.
Abstract
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"Processor-based Tailored Attestation",
Princeton University Department of Electrical Engineering Technical Report CE-L2010-005, Nov 15, 2010., 2010 .
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