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"New Models of Cache Architectures Characterizing Information Leakage from Cache Side",
Proceedings of Annual Computer Security Applications Conference (ACSAC), December 2014, pp. 96-105, 2014 .
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"Side Channel Vulnerability Metrics: the Promise and the Pitfalls",
in Proceedings of the Workshop on Hardware and Architectural Support for Security and Privacy (HASP), June 24, 2013.
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"Security Verification of Hardware-enabled Attestation Protocols",
in Proceedings of the Workshop on Hardware and Architectural Support for Security and Privacy (HASP), December 2012.
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"Stability and benefits of suboptimal utility maximization",
IEEE/ACM Transactions on Networking, vol. 19, issue 4, 2011 .
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"Securing the Dissemination of Emergency Response Data with an Integrated Hardware-Software Architecture",
2nd International Conference on Trusted Computing (TRUST 2009), Oxford, U.K., pp. 133-156, April 2009.
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"Multi-path Key Establishment Against REM Attacks in Wireless Ad Hoc Networks",
IEEE Global Communications Conference (GLOBECOM 2009), Honolulu, Hawaii, USA, Nov/Dec 2009.
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"How Bad is Suboptimal Rate Allocation?",
Proceedings of the 27th. Conference on Computer Communications, IEEE (INFOCOM ’08), pp. 951-959, April 13-18 2008.
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"Stability and Benefits of Suboptimal Utility Maximization",
submitted to IEEE Transactions on Networking, Nov. 4.
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Multi-path Key Establishment under Byzantine Attacks in Wireless Ad Hoc Networks,
, 2008 .
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"Distributed Denial of Service: Taxonomies of Attacks, Tools, and Countermeasures",
Proceedings of the ISCA 17th International Conference on Parallel and Distributed Computing Systems (PDCS 2004), International Workshop on Security in Parallel and Distributed Systems, San Francisco, California, USA, pp. 543-550, Sept. 2004.
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"Implementation Complexity of Bit Permutation Instructions",
Proceedings of the 37th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, Pacific Grove, California, USA, pp. 879-886, Nov. 2003.
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"Arbitrary Bit Permutations in One or Two Cycles",
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2003), The Hague, The Netherlands, pp. 237-247, June 2003.
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"Subword Sorting with Versatile Permutation Instructions",
Proceedings of the International Conference on Computer Design (ICCD 2002), Freiburg, Germany, pp. 234-241, Sept. 2002.
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"Bit Permutation Instructions for Accelerating Software Cryptography",
Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2000), Boston, Massachusetts, USA, pp. 138-148, July 2000.
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"Using Moving Target Defense for Secure Hardware Design",
Princeton University Department of Electrical Engineering Technical Report CE-L2016-002, 2016 .
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"Improving Cyber Security",
Advances in Cyber Security: Technology, Operations and Experiences: Fordham University Press, pp. 37-59, 2013 .
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"Processor Accelerator for AES",
Proceedings of the 2010 IEEE 8th Symposium on Application Specific Processors, Anaheim, CA, USA, pp. 71-76, June 13-14 2010.
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"Hardware Mechanisms for Memory Authentication: A Survey of Existing Techniques and Engines",
Transactions on Computational Science IV, Lecture Notes in Computer Science (LNCS), issue 5340, pp. 1-22, March 2009.
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UserMode SP_ISCA2005,
, 2005 .
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"Precision Architecture",
IEEE computer, vol. 22, issue 1, pp. 14, 01/1989.
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"Special Section on Secure Computer Architectures",
IEEE Transactions on Computers, vol. 67, issue 3, March 2018.
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"A Framework for Realizing Security on Demand in Cloud Computing",
IEEE International Conference on Cloud Computing Technology and Science (CloudCom), Bristol, UK, December 2013.
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Checking Integrity of Untrusted Data with Few Queries,
, Princeton University Department of Electrical Engineering Technical Report CE-L2007-008, September 2007.
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Efficient Randomness Generation Techniques for Embedded Systems,
, Princeton University Department of Electrical Engineering Technical Report CE-L2007-015, December 2007.
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