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1986
"Hewlett-Packard Precision Architecture: the Processor",
HP Journal, vol. 37, issue 8, pp. 19, 08/1986.
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1989
"Precision Architecture",
IEEE computer, vol. 22, issue 1, pp. 14, 01/1989.
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1999
"Efficiency of MicroSIMD Architectures and Index-Mapped Data for Media Processors",
Proceedings of Media Processors 1999 IS&T/SPIE Symposium on Electric Imaging: Science and Technology, San Jose, California, pp. 34-46, Jan. 1999.
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2000
"Fast Subword Permutation Instructions Using Omega and Flip Network Stages",
Proceedings of the International Conference on Computer Design (ICCD 2000), Austin, Texas, USA, pp. 15-22, Sept. 2000.
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"Performance Impact of Data Compression on Virtual Private Network Transactions",
Proceedings of the 25th IEEE Conference on Local Computer Networks (LCN 2000), Tampa, Florida, USA, pp. 500-510, Nov. 2000.
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"Cost-Effective Multiplication with Enhanced Adders for Multimedia Applications",
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2000), vol. 1, Geneva Switzerland, pp. 651-654, May 2000.
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"Bit Permutation Instructions for Accelerating Software Cryptography",
Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2000), Boston, Massachusetts, USA, pp. 138-148, July 2000.
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"Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures",
Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2000), Boston, Massachusetts, USA, pp. 3-14, July 2000.
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"Fast Subword Permutation Instructions Based on Butterfly Networks",
Proceedings of Media Processors IS&T/SPIE Symposium on Electric Imaging: Science and Technology, San Jose, California, pp. 80-86, Jan. 2000.
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2001
"Architectural Enhancements for Fast Subword Permutations with Repetitions in Cryptographic Applications",
Proceedings of the International Conference on Computer Design (ICCD 2001), Austin, Texas, USA, pp. 453-461, Sept. 2001.
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"Performance Impact of Addressing Modes on Encryption Algorithms",
Proceedings of the International Conference on Computer Design (ICCD 2001), Austin, Texas, USA, pp. 542-545, Sept. 2001.
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"Efficient Permutation Instructions for Fast Software Cryptography",
IEEE Micro, vol. 21, issue 6, pp. 56-69, Dec. 2001.
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"Instruction Set Architecture for Multimedia Signal Processing",
Book Chapter in Vojin G. Oklobdzija ed., The Computer Engineering Handbook: CRC Press, ISBN: 0-8493-0885-2, Invited Chapter, pp. 39-1 to 39-38, 2001 .
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"Multimedia Instructions in Microprocessors for Native Signal Processing",
Book Chapter in Yu Hen Hu, ed., Programmable Digital Signal Processors: Architecture: Programming, and Applications, New York, Marcel Dekker, Inc., ISBN: 0-8247-0647-1, pp. 91-145, 2001 .
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"Multimedia Instructions in IA-64",
Proceedings of the IEEE International Conference on Multimedia and Expo (ICME 2001), Tokyo, Japan, Aug. 2001, pp. 281-284, 2001 .
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2002
"Subword Sorting with Versatile Permutation Instructions",
Proceedings of the International Conference on Computer Design (ICCD 2002), Freiburg, Germany, pp. 234-241, Sept. 2002.
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"Workload Characterization of Elliptic Curve Cryptography and other Network Security Algorithms for Constrained Environments",
Proceedings of the 5th IEEE Annual Workshop on Workload Characterization (WWC-5), Austin, Texas, USA, pp. 127-137, Nov. 2002.
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"Refining Instruction Set Architecture for High-Performance Multimedia Processing in Constrained Environments",
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2002), San Jose, California, pp. 253-264, July 2002.
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"How a Processor can Permute n bits in O(1) cycles",
Proceedings of IEEE Hot Chips 14 - A Symposium on High Performance Chips, Stanford University, USA, Aug. 2002.
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"PLX: A Fully Subword-Parallel Instruction Set Architecture for Fast Scalable Multimedia Processing",
Proceedings of the 2002 IEEE International Conference on Multimedia and Expo (ICME 2002), Lusanne, Switzerland, pp. 117-120, Aug. 2002.
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2003
"Implementation Complexity of Bit Permutation Instructions",
Proceedings of the 37th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, Pacific Grove, California, USA, pp. 879-886, Nov. 2003.
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"Micro-Architecture Issues of Predicated Execution",
Proceedings of the 37th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, pp. 349-354, Nov. 2003.
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"Scoping Security Issues for Interactive Grids",
Proceedings of the 37th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, pp. 367-373, Nov. 2003.
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"Enlisting Hardware Architecture to Thwart Malicious Code Injection",
Proceedings of the International Conference on Security in Pervasive Computing (SPC-2003), Boppard, Germany, pp. 237-252, March 2003.
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"Architectural Techniques for Accelerating Subword Permutations with Repetitions",
IEEE Transactions on Very Large Scale Integration Systems, vol. 11, issue 3, pp. 325-335, June 2003.
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