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Filters: keyword is processor [Clear All Filters]
2003
"Architectural Techniques for Accelerating Subword Permutations with Repetitions",
IEEE Transactions on Very Large Scale Integration Systems, vol. 11, issue 3, pp. 325-335, June 2003.
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2005
"Single-Cycle Bit Permutations with MOMR Execution",
Journal of Computer Science and Technology, vol. 20, issue 5, pp. 577-585, September 2005.
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"PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing",
Journal of VLSI Signal Processing, vol. 40, issue 1, pp. 85-108, 2005 .
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2006
"Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors",
Proceedings of the 19th International Conference on VLSI Design (VLSID 2006), Hyderabad, India, IEEE Computer Society, pp. 299-304, January 2006.
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"Covert and Side Channels due to Processor Architecture",
Proceedings of the 22nd Annual Computer Security Applications Conference (ACSAC'06), pp. 473-482, December 2006.
Abstract
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2007
"Performing Advanced Bit Manipulations Efficiently in General-Purpose Processors",
Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH-18), Montpellier, France, pp. 251-260, June 2007.
Abstract
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