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Cache-collision timing attack

The detail information can be found in the paper and the source code below. The original copy from Joseph Bonneau can be found here.

Cache collision attack experiments
Attack CPU L1-D L1-I L2 Mode Algorithm Cache Evict Iterations Study Increment Min. Samples Max. Samples Median Samples Mean Samples
Success Intel T2300 32KB 32KB 2MB Encrypt Home Stretch L2 10 16 131072 327680 196608 222822.40
Success Intel Pentium M 760 32KB 32KB 2MB Encrypt Home Stretch L2 100 10 117760 687104 244736 260464.64
Success " " " " " " " " 11 65536 454656 249856 260751.36
Success " " " " " " " " 12 69632 622592 339968 335339.52
Success " " " " " " " " 13 65536 696320 319488 336117.76
Success " " " " " " " " 14 81920 638976 327680 345210.88
Success " " " " " " " " 15 98304 720896 425984 410910.72
Success " " " " " " " " 16 196608 720896 393216 400424.96
Success " " " " " " " " 17 131072 917504 524288 507248.64
Success " " " " " " " " 18 262144 1048576 786432 608174.08
Success " " " " " " " " 19 514288 1048576 524288 739246.08
Success " " " " " " " " 20 1048576 1048576 1048576 1048576
Success " " " " " " " " 21 2097152 2097152 2097152 2097152
Success " " " " " " " " 22 4194304 4194304 4194304 4194304
Success " " " " " " " " 23 8388608 8388608 8388608 8388608
Success " " " " " " " " 24 16777216 16777216 16777216 16777216
Success " " " " " " " " 25 33554432 33554432 33554432 33554432
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