PAX is a datapath-scalable, minimalist cryptographic processor architecture for mobile and wireless information appliances. The chief design goal of PAX is to enable security processing at high enough throughputs to fully utilize the high bandwidth connections offered by the existing and emerging wireless technologies. The next-generation cellular and WLAN technologies are expected to have data rates as high as 100 Mbps.
Similar to PAX-PLX 1.0, it is encoded on top of the existing encodings of PLX. Neverthless, since this is a PAX-only processor, there are no PLX instructions in this version. This version is currently under development and therefore it is not yet publicly available. PAX developers can access these documents with their download password. Please fill out this form (explanation) and email to firstname.lastname@example.org to obtain a password.
Readme for PAXToolset
The PAX Toolset is launched from the ConfigurationTool executable jar file.
1. Select root folder of source design files. By default, project source
Currently, PAX is supported by an assembler, and can be implemented on a Xilinx Virtex II Pro FPGA. More specifically, the following are suppoted by PAX:
The PAX-128 FPGA is currenlty not yet working. The PAX user manual describes how to use the PAX assembler and FPGA, and addresses the current state of progress on PAX-128.
The following documents pertaining to the PAX FPGA project are available for download: