Currently, PAX is supported by an assembler, and can be implemented on a Xilinx Virtex II Pro FPGA. More specifically, the following are suppoted by PAX:
The PAX-128 FPGA is currenlty not yet working. The PAX user manual describes how to use the PAX assembler and FPGA, and addresses the current state of progress on PAX-128.
The following documents pertaining to the PAX FPGA project are available for download:
PAX architecture and tools have been used in some of the papers published by PALMS. These are listed below:
PAX is a datapath-scalable, minimalist cryptographic processor architecture for mobile and wireless information appliances. The chief design goal of PAX is to enable security processing at high enough throughputs to fully utilize the high bandwidth connections offered by the existing and emerging wireless technologies. The next-generation cellular and WLAN technologies are expected to have data rates as high as 100 Mbps.