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Filters: author is Ruby B. Lee [Clear All Filters]
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"BitDeposit: Deterring Attacks and Abuses of Cloud Computing Services Through Economic Measures",
in Proceedings of the Workshop on Assured Cloud Computing (ACC), May 2013.
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"Architectural Support for Hypervisor-Secure Virtualization",
in Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 3–7, 2012.
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"Physical Attack Protection with Human-Secure Virtualization in Data Centers",
Workshop on Open Resilient human-aware Cyber-physical Systems (WORCS), June 25, 2012.
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"Rapid Single-Chip Secure Processor Prototyping on OpenSPARC FPGA Platform",
in Proceedings of the Rapid System Prototyping Symposium (RSP), May 24-27, 2011.
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"A Case for Hardware Protection of Guest VMs from Compromised Hypervisors in Cloud Computing",
in Proceedings of the Second International Workshop on Security and Privacy in Cloud Computing (SPCC), June 20-24, 2011.
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"Eliminating the Hypervisor Attack Surface for a More Secure Cloud",
in Proceedings of the Conference on Computer and Communications Security (CCS), Oct. 17-21, 2011.
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"Trust but Verify: Trust Evidence for Hypervisor-Secure Virtualization",
Princeton University Department of Electrical Engineering Technical Report CE-L2011-008, Nov. 16, 2011.
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"General-purpose FPGA Platform for Efficient Encryption and Hashing",
in Proceedings of the Application-specific Systems, Architectures and Processors conference, ASAP, July 7-9, 2010.
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"A Framework for Testing Hardware-Software Security Architectures",
Annual Computer Security Applications Conference, Austin, Texas USA, December 6 2010.
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"Evaluation of OpenSPARC FPGA Platform as a Security and Performance Research Platform",
Princeton University Department of Electrical Engineering Technical Report CE-L2010-002, Sept. 6, 2010.
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"A Framework for Testing Hardware-Software Security Architectures",
Princeton University Department of Electrical Engineering Technical Report CE-L2009-001, February 2009.
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"SP Reference Manual Addendum -- Secure Stacks for TSMs and Emulation of SP Interrupt Protection",
Princeton University Department of Electrical Engineering Technical Report CE-L2009-006, August 2009.
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"Framework for Design Validation of Security Architectures",
Princeton University Department of Electrical Engineering Technical Report CE-L2008-013, November 2008.
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"SecureCore Prototype/Demo Manual",
Princeton University Department of Electrical Engineering Technical Report CE-L2008-009, August 2008.
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"SP Processor Architecture Reference Manual",
Princeton University Department of Electrical Engineering Technical Report CE-L2008-008, August 2008.
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"Cloud Server Benchmark Suite for Evaluating New Hardware Architectures",
IEEE Computer Architecture Letters, July-Dec 2016.
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"Smartphone Impostor Detection with Behavioral Data Privacy and Minimalist Hardware Support",
TinyML Research Symposium, 2021 .
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"SoK: Hardware Defenses Against Speculative Execution Attacks",
IEEE International Symposium on Secure and Private Execution Environment Design, 2021 .
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"Butterfly and inverse Butterfly nets integration on Altera NioS-ii embedded processor",
44th IEEE Asilomar Conference on Signal, Systems and Computers, Pacific Grove, California, USA, November 2010.
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"Virtualization of a Processor-based Crypto-Protection Mechanism and Integration within a Separation Kernel Architecture",
Princeton University Department of Electrical Engineering Technical Report CE-L2006-006, November 2006.
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"Newcache: secure cache architecture thwarting cache side channel attacks",
IEEE Micro Special Issues on Security, vol. 36, issue 5, Sept/Oct 2016.
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"Last-Level Cache Side-Channel Attacks are Practical",
Proceedings of IEEE Symposium on Security and Privacy, San Jose, pp. 605-622, May 2015.
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"Can randomized mapping secure instruction caches from side-channel attacks?",
in Proceedings of the Workshop on Hardware and Architectural Support for Security and Privacy (HASP), Portland, June 13, 2015.
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"Random Fill Cache Architecture",
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture (Micro-47), Cambridge, pp. 203-215, December 2014.
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"Security Testing of a Secure Cache Design",
in Proceedings of the Workshop on Hardware and Architectural Support for Security and Privacy (HASP), June 24, 2013.
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