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Conference Paper
"The Reduced Address Space for Application Memory Authentication",
Proceedings of the 11th Information Security Conference (ISC'08), September 2008.
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"Architecture for a Non-Copyable Disk (NCdisk) Using a Secret-Protection (SP) SoC Solution",
Signals, Systems and Computers, 2007. ACSSC 2007. Conference Record of the Forty-First Asilomar Conference on, Pacific Grove, CA, USA, pp. 1999-2003, 11/04/2007.
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"Hardware-rooted Trust for Secure Key Management and Transient Trust",
ACM Conference on Computer and Communications Security (CCS) 2007, Alexandria, VA, pp. 389-400, October 2007.
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"Mutual Anonymous Communications: A New Covert Channel Based on Splitting Tree MAC",
IEEE Infocom 2007, pp. 2531-2535, May 6-12, 2007.
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"New Cache Designs for Thwarting Software Cache-based Side Channel Attacks",
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), San Diego, CA, pp. 494 - 505, June 2007.
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"Performing Advanced Bit Manipulations Efficiently in General-Purpose Processors",
Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH-18), Montpellier, France, pp. 251-260, June 2007.
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"Re-examining Probabilistic Versus Deterministic Key Management",
Proceedings of the 2007 IEEE International Symposium on Information Theory (ISIT), Nice, France, pp. 2586-2590, June 2007.
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"Secure Key Management Architecture Against Sensor-node Fabrication Attacks",
IEEE GlobeCom 2007, Washington, DC, November 2007.
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"TEC-Tree: A Low Cost, Parallelizable Tree for Efficient Defense against Memory Replay Attacks",
Proc. Workshop on Cryptographic Hardware and Embedded Systems (CHES 2007), Vienna, Austria, pp. 289-302, September 2007.
Abstract
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"A refined look at Bernstein's AES side-channel analysis",
Fast abstract in the Proceedings of the 2006 ACM Symposium on Information, Computer and Communications Security (ASIACCS 2006), Taipei, Taiwan, ACM, pp. 369, March 2006.
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"Covert and Side Channels due to Processor Architecture",
Proceedings of the 22nd Annual Computer Security Applications Conference (ACSAC'06), pp. 473-482, December 2006.
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"Fast Bit Compression and Expansion with Parallel Extract and Parallel Deposit Instructions",
Proceedings of the IEEE 17th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), pp. 65-72, 11/09/2006.
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"Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors",
Proceedings of the 19th International Conference on VLSI Design (VLSID 2006), Hyderabad, India, IEEE Computer Society, pp. 299-304, January 2006.
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"Scope of DDoS Countermeasures: Taxonomy of Proposed Solutions and Design Goals for Real-World Deployment",
8th International Symposium on Systems and Information Security (SSI'2006), November 2006.
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"Satisfiability-based Framework for Enabling Side-channel Attacks on Cryptographic Software",
Proceedings of the Conference on Design, Automation and Test in Europe (DATE 2006), Munich, Germany, pp. 18-23, March 2006.
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"A Traitor Tracing Scheme Based on RSA for Fast Decryption",
Proceedings of the International Conference on Applied Cryptography and Network Security (ACNS 2005), Lecture Notes in Computer Science, vol. 3531, New York, USA, Springer-Verlag, pp. 56-74, June 7-10, 2005.
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"Architecture for Protecting Critical Secrets in Microprocessors",
Proceedings of the 32nd International Symposium on Computer Architecture (ISCA 2005), Madison, Wisconsin, USA, pp. 2-13, June 4-8, 2005.
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"Architectural Enhancements for Secure Embedded Processing",
Proceedings of the NATO Advanced Research Workshop "Security and Embedded Systems", Patras, Greeece, Aug. 2005.
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"Capacity Estimation of Non-Synchronous Covert Channels",
Proceedings of the 2nd International Workshop on Security in Distributed Computing Systems (SDCS 2005), Columbus, OH, USA, pp. 170-176, June 6-9, 2005.
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"Design and Analysis of Password-Based Key Derivation Functions",
IEEE Transactions on Information Theory, vol. 51, no. 9, pp.3292-3297, Sept. 2005, and Proceedings of the Cryptographers' Track at the RSA Conference (CT-RSA 2005), Lecture Notes in Computer Science, vol. 3376, San Francisco, California, USA, pp. 245-261, Feb. 2005.
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"Enhancing Security through Hardware-assisted Run-time Validation of Program Data Properties",
Proceedings of ACM/IEEE International Conference on Hardware Software Co-design and System Synthesis (CODES+ISSS 2005), New York, USA, pp. 190-195, Sept. 2005.
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"Fast Parallel Table Lookups to Accelerate Symmetric-Key Cryptography",
Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC 2005), Las Vegas, Nevada, USA, pp. 526-531, April 4-6, 2005.
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"New Constructive Approach to Covert Channel Modeling and Channel Capacity Estimation",
Proceedings of the 8th Information Security Conference (ISC 2005), Singapore, pp. 498-505, September 2005.
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"On-Chip Lookup Tables for Fast Symmetric-Key Encryption",
Proceedings of the IEEE 16th International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2005), Samos, Greece, pp. 356-363, July 23-25, 2005.
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"Protecting Cryptographic Keys and Computations via Virtual Secure Coprocessing",
Computer Architecture News, vol. 33., no. 1, pp. 16-26, March 2005, and Proceedings of the Workshop on Architectural Support for Security and Antivirus (WASSA 2004), Boston, Massachusetts, USA, Oct. 9-13, 2004.
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