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"Aiding Side-channel Attacks on Cryptographic Software with Satisfiability-based Analysis",
IEEE Transactions on VLSI, vol. 15, issue 4, pp. 465-470, April 2007.
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"Satisfiability-based Framework for Enabling Side-channel Attacks on Cryptographic Software",
Proceedings of the Conference on Design, Automation and Test in Europe (DATE 2006), Munich, Germany, pp. 18-23, March 2006.
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"Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors",
Proceedings of the 19th International Conference on VLSI Design (VLSID 2006), Hyderabad, India, IEEE Computer Society, pp. 299-304, January 2006.
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"Maya: A Novel Block Encryption Function",
International Workshop on Coding and Cryptography (WCC 2009), Ullensvang, Norway, May 2009.
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"Protecting Cryptographic Keys and Computations via Virtual Secure Coprocessing",
Computer Architecture News, vol. 33., no. 1, pp. 16-26, March 2005, and Proceedings of the Workshop on Architectural Support for Security and Antivirus (WASSA 2004), Boston, Massachusetts, USA, Oct. 9-13, 2004.
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"A Traitor Tracing Scheme Based on RSA for Fast Decryption",
Proceedings of the International Conference on Applied Cryptography and Network Security (ACNS 2005), Lecture Notes in Computer Science, vol. 3531, New York, USA, Springer-Verlag, pp. 56-74, June 7-10, 2005.
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"Architectural Techniques for Accelerating Subword Permutations with Repetitions",
IEEE Transactions on Very Large Scale Integration Systems, vol. 11, issue 3, pp. 325-335, June 2003.
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"A Processor Architecture Defense against Buffer Overflow Attacks",
Proceedings of the IEEE International Conference on Information Technology: Research and Education (ITRE 2003), Newark, New Jersey, USA, pp. 243-250, Aug. 2003.
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"Architectural Enhancements for Fast Subword Permutations with Repetitions in Cryptographic Applications",
Proceedings of the International Conference on Computer Design (ICCD 2001), Austin, Texas, USA, pp. 453-461, Sept. 2001.
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"Performance Impact of Data Compression on Virtual Private Network Transactions",
Proceedings of the 25th IEEE Conference on Local Computer Networks (LCN 2000), Tampa, Florida, USA, pp. 500-510, Nov. 2000.
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"Hewlett-Packard Precision Architecture: the Processor",
HP Journal, vol. 37, issue 8, pp. 19, 08/1986.
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Decimation Tools Set,
, Princeton University Department of Electrical Engineering Technical Report CE-L2007-014, November 2007.
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PAX: A Cryptographic Processor with Parallel Table Lookup and Wordsize Scalability,
, Princeton University Department of Electrical Engineering Technical Report CE-L2007-010, November 2007.
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Resolving Encoding Issues in Combining PAX and PLX Instruction Sets,
, Princeton University Department of Electrical Engineering Technical Report CE-L2007-007, August 2007.
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"Single-Cycle Bit Permutations with MOMR Execution",
Journal of Computer Science and Technology, vol. 20, issue 5, pp. 577-585, September 2005.
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"Architecture for Protecting Critical Secrets in Microprocessors",
Proceedings of the 32nd International Symposium on Computer Architecture (ISCA 2005), Madison, Wisconsin, USA, pp. 2-13, June 4-8, 2005.
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"PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing",
Journal of VLSI Signal Processing, vol. 40, issue 1, pp. 85-108, 2005 .
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"Validating Word-oriented Processors for Bit and Multi-Word Operations",
Proceedings of the Asia-Pacific Computer Systems Architecture Conference (ACSAC 2004), Beijing, China, pp. 473-488, Sept. 2004.
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"On Permutation Operations in Cipher Design",
Proceedings of the International Conference on Information Technology (ITCC 2004), Las Vegas, Nevada, USA, pp. 569-577, April 5-7, 2004.
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"Permutation Operations in Block Ciphers",
Book chapter in Nadia Nedjah and Luiza de Macedo Mourelle eds., Embedded Cryptographic Hardware: Design and Security, New York, Nova Science Publisher, ISBN: 1-59454-145-0, Chapter 13, pp. 219-236, 2004 .
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"Enlisting Hardware Architecture to Thwart Malicious Code Injection",
Proceedings of the International Conference on Security in Pervasive Computing (SPC-2003), Boppard, Germany, pp. 237-252, March 2003.
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"Refining Instruction Set Architecture for High-Performance Multimedia Processing in Constrained Environments",
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2002), San Jose, California, pp. 253-264, July 2002.
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"How a Processor can Permute n bits in O(1) cycles",
Proceedings of IEEE Hot Chips 14 - A Symposium on High Performance Chips, Stanford University, USA, Aug. 2002.
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"PLX: A Fully Subword-Parallel Instruction Set Architecture for Fast Scalable Multimedia Processing",
Proceedings of the 2002 IEEE International Conference on Multimedia and Expo (ICME 2002), Lusanne, Switzerland, pp. 117-120, Aug. 2002.
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"Multimedia Instructions in Microprocessors for Native Signal Processing",
Book Chapter in Yu Hen Hu, ed., Programmable Digital Signal Processors: Architecture: Programming, and Applications, New York, Marcel Dekker, Inc., ISBN: 0-8247-0647-1, pp. 91-145, 2001 .
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